Компания Sony запатентовала очередную технологию, которая позволит графическому процессору обрабатывать сцены, состоящие из несколько миллионов полигонов в секунду. Полностью описание патента вы можете найти чуть ниже на языке оригинала:
...BACKGROUND OF THE INVENTION
[0002] The present invention relates to a serial operation pipeline suitable for an application requiring a discrete operation in which the amount to be operated on expands extemporaneously and explosively, for example, an application for expressing a frequently moving object by computer graphics, and structural elements thereof.
[0003] The serial operation pipeline sequentially conducts different operations, such as a command retrieve operation, a command decode operation or a command execute operation, at the same time, thereby increasing processing speed.
[0004] The pipeline comprises computing units that deal with a small number of command groups, and the units are connected to each other in a cascade fashion. The combination of the plural computing units to be used is appropriately changed so as to realize various processing, such as addition, subtraction and multiplication, a floating-point operation, comparison, Boolean algebra, or select (IF statement).
[0005] In making computer graphics, many kinds of discrete operations are normally conducted, such as operations within a two-dimensional pixel or between pixels, collision detection, object creation or composition, or geometry operation. In such an application, when only the main CPU of a computer is employed, a large amount of computing power is required which cannot be obtained by a computer having a single CPU. For example, a rendering process capacity of the order of several hundreds [Mpolygon/sec] and several tens [Gpixel/sec] is frequently required.
[0006] For that reason, a special-purpose processor into which an operation pipeline is installed has been employed up to now.
[0007] Most of the conventional processors of this type are made up of a single device, and a plurality of operation pipelines are installed in parallel into the processor in accordance with an estimated amount of operation. A given function is fixedly allocated to each of individual computing units that form the operation pipelines, referred to as so-called "one computing unit with one function". A pipeline using one computing unit with one function is very suitable for, for example, an application that processes the data size of a fixed length by a short throughput.
[0008] However, it is difficult to apply one computing unit with one function for various purposes. For example, in the case where the pipeline structure is changed in accordance with the intended purpose, it is necessary to additionally provide a selector (bus) for connecting a path of data to be subjected to an operation and an allocated function. For that reason, the computing units or the operation pipelines are restrictively disposed in parallel within a single device. Also, when at least a regular number of the computing units or the operation pipelines are disposed in parallel, they are prevented from being clustered, and a control and a data path (cash or bus) are required for preventing the cluster, respectively, thereby leading to the deterioration of the integration efficiency.
[0009] In order to cope with a variety of applications, it is proposed to structure a programmable data flow graph (DFG). However, the programmable DFG is relatively high in the occupied ratio of non-operation elements, such as the selector, with respect to the computing unit. It has been well known that the ratio becomes higher as the programmability of the operation becomes more enhanced. Also, it is difficult to always execute all the functions of the programmable DFG because the functions are divided into sub-functions. In order to enhance the execution efficiency, the functions must be brought into function blocks, the object of which are fixed to some degree, and become improper for applications that process various types of data.
[0010] On the other hand, it is proposed to arrange the computing units in parallel two-dimensionally from the viewpoint of ensuring higher operation capacity. Two-dimensional parallel means that the computing units are arranged in parallel and in a cascade fashion. That is, data flows are arranged in parallel due to deep pipelines. As a special implement, there are rendering pipelines that are disposed in parallel. In making the two-dimensional parallel, only necessary functions are supplied within the pipelines, and the programmability is removed as much as possible, thereby enhancing the efficiency by the cascade connection of the exclusive computing units.
[0011] In the future, the need for diversification of discrete operations is expected to grow. In such case, there is desired a general-purpose pipeline that realizes a complicated processing flow with an extemporaneous and explosive amount of operations with respect to various data sizes. In order to structure the general-purpose operation pipelines, it is required that the data path be simple (linear), and that cascade connections be made without uselessness. Also, a construction that can realize various operations by one computing unit is required.
SUMMARY OF THE INVENTION
[0012] The present invention has been made under the above circumstances, and therefore an object of the present invention is to realize various operations by one computing unit without increasing the costs... |
